Most modern day computer systems require the transmission of data between physically spaced subsystems. In synchronous systems, all data processing must be performed in synchronization with clock cycles generated by a system clock. As computer systems are designed to operate at faster and faster speeds of operation, the clock cycle times have become very short in duration such that the time required to transmit data between subsystems plus clock skew throughout the computer system can be longer than the cycle time. Accordingly, data transmission between subsystems may be asynchronous relative to the clock cycles of the receiving subsystem.
It is, therefore, imperative to provide high performance data transmission devices to synchronize data received by a subsystem to the clock cycles of the receiving subsystem. One known method of transmitting data is the "asynchronous" method. Pursuant to this method, a clock signal is transmitted with data from one subsystem to another subsystem. The transmitted clock signal is input to a synchronizer arranged within the receiving subsystem to make the transmitted clock signal synchronous with the clock cycles operating within the receiving subsystem. The receiving subsystem must wait for the synchronizer to resolve a synchronous relationship between the transmitted clock and the clock cycle operation within the receiving subsystem and then uses the data. A problem with the asynchronous method is that the cycle time must be at least as long as the synchronizer resolving time. The reliability of synchronizers increases with increasing resolving time. Thus, high system clock frequencies cause short cycle times thereby limiting the resolving time and reducing the reliability of the synchronizer.
Another well known method of transmitting data between subsystems is to send a block of data together with a clock signal from the transmitting subsystem. The block of data is loaded into a buffer within the receiving subsystem by the transmitted clock. A signal is generated as the buffer begins to be loaded with the transmitted block of data. This signal is sent through a synchronizer. After the resolution of the signal to be synchronous with the receiving system clock, the receiving subsystem knows from the now synchronized signal that a block of data has been loaded into the buffer and begins to unload the buffer synchronously with its clock cycles.
The data block method permits high speed data transmission while allowing a long resolution time for synchronizing the signal which indicates the beginning of loading of the block of data into the buffer. However, the delay in the transmission path (i.e. the time from when the first data item of the block of data arrived at the buffer until the time such first data item can be processed in the receiving subsystem) includes the synchronizer resolving time. Accordingly, the delay time can be long if the resolving time is kept long to improve the reliability of the synchronizer.